90 lines
2.0 KiB
NASM
90 lines
2.0 KiB
NASM
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; chenillarEssai3.asm
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;
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; Created: 19-03-18 13:13:56
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; Author : Adrien
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;
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.dseg
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.def rtmp = r16
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.def rdec = r17
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.def rsens = r18
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.cseg
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.include "m328pdef.inc"
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.org 0x0000
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jmp RESET
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.org OC0Aaddr
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jmp TIM0_COMPA ; Timer0 CompareA
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.org OVF0addr
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jmp TIM0_OVF
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.org 0x0100
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RESET:
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ldi rtmp, HIGH(RAMEND) ;Charge la valeur haute de l?adresse en fin m?moire RAM
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out SPH, rtmp ;Positionne le pointeur de pile haut sur cette adresse
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ldi rtmp, LOW(RAMEND) ;Charge la valeur basse de l?adresse en fin m?moire RAM
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out SPL, rtmp ;Positionne le pointeur de pile bas sur cette adresse
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; Replace with your application code
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ser rtmp ;Port en sortie (les bits du port sont mis ? 1, soit en sortie)
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out DDRD, rtmp ;Ecriture sur le
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clr rtmp ;Port en bas (les bits du port sont mis ? 0, Led ?teinte)
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ldi rtmp, 0x01
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out PORTD, rtmp ;PINB1 Mis ? 1
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clr rsens
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;_____________________________________________________________________________
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;Setup Timer0
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;_____________________________________________________________________________
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CLR rtmp
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OUT TCCR0A, rtmp ;Normal port op
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LDI rtmp, 0x01
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OUT TCCR0B, rtmp ; No Force, No wave, Clk from precal/1024, 7.8125Khz, 128?s
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ldi rtmp, 0x02
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sts TIMSK0, rtmp ; OCR0A Interrupt Enable
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CLR rtmp
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OUT TCNT0, rtmp ;
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LDI rtmp, 0xff
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OUT OCR0A, rtmp ; 256*128?s = 16ms
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LDI rdec, 0xFF
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;_____________________________________________________________________________
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;Setup PWM Timer0
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;_____________________________________________________________________________
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SEI
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start:
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nop
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nop
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nop
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jmp PC-2
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TIM0_COMPA:
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dec rdec
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BRNE PC+7
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in rtmp, PORTD
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lsl rtmp ;Shift left
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BRCC PC+2; Si le cary est ? 0 rtmp est dif de 0x00 Si carry est ? 1, rtmp = 0x00 donc on le met ? 0x01
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ldi rtmp, 0x01
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out PORTD, rtmp
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ldi r18, 0xff
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ldi rtmp, 0x00
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out TCNT0, rtmp
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reti ;Fin de l?interruption
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TIM0_OVF:
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dec rdec
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BRNE PC+1
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in rtmp, PORTD
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lsl rtmp ;Shift left
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BRCC PC+2; Si le cary est ? 0 rtmp est dif de 0x00 Si carry est ? 1, rtmp = 0x00 donc on le met ? 0x01
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ldi rtmp, 0x01
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out PORTD, rtmp
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reti |