1890 lines
118 KiB
Plaintext
1890 lines
118 KiB
Plaintext
|
||
AVRASM ver. 2.2.7 C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm Sun Jun 10 10:18:03 2018
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[builtin](2): Including file 'C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.2.150\avrasm\inc\m328pdef.inc'
|
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(34): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\vectors.asm'
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(35): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\hd44780.asm'
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\hd44780.asm(7): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\hd44780.inc'
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\hd44780.asm(29): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\div8u.asm'
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\div8u.asm(6): warning: Register r16 already defined by the .DEF directive
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\hd44780.asm(29): 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\div8u.asm' included form here
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(35): 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\hd44780.asm' included form here
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(36): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\wait.asm'
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(37): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\1-wire.asm'
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\1-wire.asm(9): warning: Register r17 already defined by the .DEF directive
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(37): 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\1-wire.asm' included form here
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(38): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\crc8.asm'
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[builtin](2): Including file 'C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATmega_DFP\1.2.150\avrasm\inc\m328pdef.inc'
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(34): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\vectors.asm'
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(35): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\hd44780.asm'
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\hd44780.asm(7): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\hd44780.inc'
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\hd44780.asm(29): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\div8u.asm'
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(36): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\wait.asm'
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(37): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\1-wire.asm'
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C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(38): Including file 'C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\crc8.asm'
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;------------------------------------------------------------------------------
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;***** Created: 2011-02-09 12:03 ******* Source: ATmega328P.xml **********
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "m328Pdef.inc"
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;* Title : Register/Bit Definitions for the ATmega328P
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;* Date : 2011-02-09
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;* Version : 2.35
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;* Support E-mail : avr@atmel.com
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;* Target MCU : ATmega328P
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _M328PDEF_INC_
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#define _M328PDEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device ATmega328P
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#pragma AVRPART ADMIN PART_NAME ATmega328P
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x95
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.equ SIGNATURE_002 = 0x0f
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#pragma AVRPART CORE CORE_VERSION V2E
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ UDR0 = 0xc6 ; MEMORY MAPPED
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.equ UBRR0L = 0xc4 ; MEMORY MAPPED
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.equ UBRR0H = 0xc5 ; MEMORY MAPPED
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.equ UCSR0C = 0xc2 ; MEMORY MAPPED
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.equ UCSR0B = 0xc1 ; MEMORY MAPPED
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.equ UCSR0A = 0xc0 ; MEMORY MAPPED
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.equ TWAMR = 0xbd ; MEMORY MAPPED
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.equ TWCR = 0xbc ; MEMORY MAPPED
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.equ TWDR = 0xbb ; MEMORY MAPPED
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.equ TWAR = 0xba ; MEMORY MAPPED
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.equ TWSR = 0xb9 ; MEMORY MAPPED
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.equ TWBR = 0xb8 ; MEMORY MAPPED
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.equ ASSR = 0xb6 ; MEMORY MAPPED
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.equ OCR2B = 0xb4 ; MEMORY MAPPED
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.equ OCR2A = 0xb3 ; MEMORY MAPPED
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.equ TCNT2 = 0xb2 ; MEMORY MAPPED
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.equ TCCR2B = 0xb1 ; MEMORY MAPPED
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.equ TCCR2A = 0xb0 ; MEMORY MAPPED
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.equ OCR1BL = 0x8a ; MEMORY MAPPED
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.equ OCR1BH = 0x8b ; MEMORY MAPPED
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.equ OCR1AL = 0x88 ; MEMORY MAPPED
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.equ OCR1AH = 0x89 ; MEMORY MAPPED
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.equ ICR1L = 0x86 ; MEMORY MAPPED
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.equ ICR1H = 0x87 ; MEMORY MAPPED
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.equ TCNT1L = 0x84 ; MEMORY MAPPED
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.equ TCNT1H = 0x85 ; MEMORY MAPPED
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.equ TCCR1C = 0x82 ; MEMORY MAPPED
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.equ TCCR1B = 0x81 ; MEMORY MAPPED
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.equ TCCR1A = 0x80 ; MEMORY MAPPED
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.equ DIDR1 = 0x7f ; MEMORY MAPPED
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.equ DIDR0 = 0x7e ; MEMORY MAPPED
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.equ ADMUX = 0x7c ; MEMORY MAPPED
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.equ ADCSRB = 0x7b ; MEMORY MAPPED
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.equ ADCSRA = 0x7a ; MEMORY MAPPED
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.equ ADCH = 0x79 ; MEMORY MAPPED
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.equ ADCL = 0x78 ; MEMORY MAPPED
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.equ TIMSK2 = 0x70 ; MEMORY MAPPED
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.equ TIMSK1 = 0x6f ; MEMORY MAPPED
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.equ TIMSK0 = 0x6e ; MEMORY MAPPED
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.equ PCMSK1 = 0x6c ; MEMORY MAPPED
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.equ PCMSK2 = 0x6d ; MEMORY MAPPED
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.equ PCMSK0 = 0x6b ; MEMORY MAPPED
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.equ EICRA = 0x69 ; MEMORY MAPPED
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.equ PCICR = 0x68 ; MEMORY MAPPED
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.equ OSCCAL = 0x66 ; MEMORY MAPPED
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.equ PRR = 0x64 ; MEMORY MAPPED
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.equ CLKPR = 0x61 ; MEMORY MAPPED
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.equ WDTCSR = 0x60 ; MEMORY MAPPED
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.equ SREG = 0x3f
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.equ SPL = 0x3d
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.equ SPH = 0x3e
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.equ SPMCSR = 0x37
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.equ MCUCR = 0x35
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.equ MCUSR = 0x34
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.equ SMCR = 0x33
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.equ ACSR = 0x30
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.equ SPDR = 0x2e
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.equ SPSR = 0x2d
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.equ SPCR = 0x2c
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.equ GPIOR2 = 0x2b
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.equ GPIOR1 = 0x2a
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.equ OCR0B = 0x28
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.equ OCR0A = 0x27
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.equ TCNT0 = 0x26
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.equ TCCR0B = 0x25
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.equ TCCR0A = 0x24
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.equ GTCCR = 0x23
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.equ EEARH = 0x22
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.equ EEARL = 0x21
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.equ EEDR = 0x20
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.equ EECR = 0x1f
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.equ GPIOR0 = 0x1e
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.equ EIMSK = 0x1d
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.equ EIFR = 0x1c
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.equ PCIFR = 0x1b
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.equ TIFR2 = 0x17
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.equ TIFR1 = 0x16
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.equ TIFR0 = 0x15
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.equ PORTD = 0x0b
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.equ DDRD = 0x0a
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.equ PIND = 0x09
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.equ PORTC = 0x08
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.equ DDRC = 0x07
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.equ PINC = 0x06
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.equ PORTB = 0x05
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.equ DDRB = 0x04
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.equ PINB = 0x03
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; ***** BIT DEFINITIONS **************************************************
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; ***** USART0 ***********************
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; UDR0 - USART I/O Data Register
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.equ UDR0_0 = 0 ; USART I/O Data Register bit 0
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.equ UDR0_1 = 1 ; USART I/O Data Register bit 1
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.equ UDR0_2 = 2 ; USART I/O Data Register bit 2
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.equ UDR0_3 = 3 ; USART I/O Data Register bit 3
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.equ UDR0_4 = 4 ; USART I/O Data Register bit 4
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.equ UDR0_5 = 5 ; USART I/O Data Register bit 5
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.equ UDR0_6 = 6 ; USART I/O Data Register bit 6
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.equ UDR0_7 = 7 ; USART I/O Data Register bit 7
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; UCSR0A - USART Control and Status Register A
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.equ MPCM0 = 0 ; Multi-processor Communication Mode
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.equ U2X0 = 1 ; Double the USART transmission speed
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.equ UPE0 = 2 ; Parity Error
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.equ DOR0 = 3 ; Data overRun
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.equ FE0 = 4 ; Framing Error
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.equ UDRE0 = 5 ; USART Data Register Empty
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.equ TXC0 = 6 ; USART Transmitt Complete
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.equ RXC0 = 7 ; USART Receive Complete
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; UCSR0B - USART Control and Status Register B
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.equ TXB80 = 0 ; Transmit Data Bit 8
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.equ RXB80 = 1 ; Receive Data Bit 8
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.equ UCSZ02 = 2 ; Character Size
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.equ TXEN0 = 3 ; Transmitter Enable
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.equ RXEN0 = 4 ; Receiver Enable
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.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable
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.equ TXCIE0 = 6 ; TX Complete Interrupt Enable
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.equ RXCIE0 = 7 ; RX Complete Interrupt Enable
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; UCSR0C - USART Control and Status Register C
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.equ UCPOL0 = 0 ; Clock Polarity
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.equ UCSZ00 = 1 ; Character Size
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.equ UCPHA0 = UCSZ00 ; For compatibility
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.equ UCSZ01 = 2 ; Character Size
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.equ UDORD0 = UCSZ01 ; For compatibility
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.equ USBS0 = 3 ; Stop Bit Select
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.equ UPM00 = 4 ; Parity Mode Bit 0
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.equ UPM01 = 5 ; Parity Mode Bit 1
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.equ UMSEL00 = 6 ; USART Mode Select
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.equ UMSEL0 = UMSEL00 ; For compatibility
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.equ UMSEL01 = 7 ; USART Mode Select
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.equ UMSEL1 = UMSEL01 ; For compatibility
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; UBRR0H - USART Baud Rate Register High Byte
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.equ UBRR8 = 0 ; USART Baud Rate Register bit 8
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.equ UBRR9 = 1 ; USART Baud Rate Register bit 9
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.equ UBRR10 = 2 ; USART Baud Rate Register bit 10
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.equ UBRR11 = 3 ; USART Baud Rate Register bit 11
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; UBRR0L - USART Baud Rate Register Low Byte
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.equ _UBRR0 = 0 ; USART Baud Rate Register bit 0
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||
.equ _UBRR1 = 1 ; USART Baud Rate Register bit 1
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.equ UBRR2 = 2 ; USART Baud Rate Register bit 2
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||
.equ UBRR3 = 3 ; USART Baud Rate Register bit 3
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||
.equ UBRR4 = 4 ; USART Baud Rate Register bit 4
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||
.equ UBRR5 = 5 ; USART Baud Rate Register bit 5
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||
.equ UBRR6 = 6 ; USART Baud Rate Register bit 6
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.equ UBRR7 = 7 ; USART Baud Rate Register bit 7
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||
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||
|
||
; ***** TWI **************************
|
||
; TWAMR - TWI (Slave) Address Mask Register
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||
.equ TWAM0 = 1 ;
|
||
.equ TWAMR0 = TWAM0 ; For compatibility
|
||
.equ TWAM1 = 2 ;
|
||
.equ TWAMR1 = TWAM1 ; For compatibility
|
||
.equ TWAM2 = 3 ;
|
||
.equ TWAMR2 = TWAM2 ; For compatibility
|
||
.equ TWAM3 = 4 ;
|
||
.equ TWAMR3 = TWAM3 ; For compatibility
|
||
.equ TWAM4 = 5 ;
|
||
.equ TWAMR4 = TWAM4 ; For compatibility
|
||
.equ TWAM5 = 6 ;
|
||
.equ TWAMR5 = TWAM5 ; For compatibility
|
||
.equ TWAM6 = 7 ;
|
||
.equ TWAMR6 = TWAM6 ; For compatibility
|
||
|
||
; TWBR - TWI Bit Rate register
|
||
.equ TWBR0 = 0 ;
|
||
.equ TWBR1 = 1 ;
|
||
.equ TWBR2 = 2 ;
|
||
.equ TWBR3 = 3 ;
|
||
.equ TWBR4 = 4 ;
|
||
.equ TWBR5 = 5 ;
|
||
.equ TWBR6 = 6 ;
|
||
.equ TWBR7 = 7 ;
|
||
|
||
; TWCR - TWI Control Register
|
||
.equ TWIE = 0 ; TWI Interrupt Enable
|
||
.equ TWEN = 2 ; TWI Enable Bit
|
||
.equ TWWC = 3 ; TWI Write Collition Flag
|
||
.equ TWSTO = 4 ; TWI Stop Condition Bit
|
||
.equ TWSTA = 5 ; TWI Start Condition Bit
|
||
.equ TWEA = 6 ; TWI Enable Acknowledge Bit
|
||
.equ TWINT = 7 ; TWI Interrupt Flag
|
||
|
||
; TWSR - TWI Status Register
|
||
.equ TWPS0 = 0 ; TWI Prescaler
|
||
.equ TWPS1 = 1 ; TWI Prescaler
|
||
.equ TWS3 = 3 ; TWI Status
|
||
.equ TWS4 = 4 ; TWI Status
|
||
.equ TWS5 = 5 ; TWI Status
|
||
.equ TWS6 = 6 ; TWI Status
|
||
.equ TWS7 = 7 ; TWI Status
|
||
|
||
; TWDR - TWI Data register
|
||
.equ TWD0 = 0 ; TWI Data Register Bit 0
|
||
.equ TWD1 = 1 ; TWI Data Register Bit 1
|
||
.equ TWD2 = 2 ; TWI Data Register Bit 2
|
||
.equ TWD3 = 3 ; TWI Data Register Bit 3
|
||
.equ TWD4 = 4 ; TWI Data Register Bit 4
|
||
.equ TWD5 = 5 ; TWI Data Register Bit 5
|
||
.equ TWD6 = 6 ; TWI Data Register Bit 6
|
||
.equ TWD7 = 7 ; TWI Data Register Bit 7
|
||
|
||
; TWAR - TWI (Slave) Address register
|
||
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit
|
||
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0
|
||
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1
|
||
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2
|
||
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3
|
||
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4
|
||
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5
|
||
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6
|
||
|
||
|
||
; ***** TIMER_COUNTER_1 **************
|
||
; TIMSK1 - Timer/Counter Interrupt Mask Register
|
||
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable
|
||
.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable
|
||
.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable
|
||
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
|
||
|
||
; TIFR1 - Timer/Counter Interrupt Flag register
|
||
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag
|
||
.equ OCF1A = 1 ; Output Compare Flag 1A
|
||
.equ OCF1B = 2 ; Output Compare Flag 1B
|
||
.equ ICF1 = 5 ; Input Capture Flag 1
|
||
|
||
; TCCR1A - Timer/Counter1 Control Register A
|
||
.equ WGM10 = 0 ; Waveform Generation Mode
|
||
.equ WGM11 = 1 ; Waveform Generation Mode
|
||
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
|
||
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
|
||
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
|
||
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
|
||
|
||
; TCCR1B - Timer/Counter1 Control Register B
|
||
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
|
||
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
|
||
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
|
||
.equ WGM12 = 3 ; Waveform Generation Mode
|
||
.equ WGM13 = 4 ; Waveform Generation Mode
|
||
.equ ICES1 = 6 ; Input Capture 1 Edge Select
|
||
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
|
||
|
||
; TCCR1C - Timer/Counter1 Control Register C
|
||
.equ FOC1B = 6 ;
|
||
.equ FOC1A = 7 ;
|
||
|
||
; GTCCR - General Timer/Counter Control Register
|
||
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
.equ TSM = 7 ; Timer/Counter Synchronization Mode
|
||
|
||
|
||
; ***** TIMER_COUNTER_2 **************
|
||
; TIMSK2 - Timer/Counter Interrupt Mask register
|
||
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable
|
||
.equ TOIE2A = TOIE2 ; For compatibility
|
||
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable
|
||
.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable
|
||
|
||
; TIFR2 - Timer/Counter Interrupt Flag Register
|
||
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag
|
||
.equ OCF2A = 1 ; Output Compare Flag 2A
|
||
.equ OCF2B = 2 ; Output Compare Flag 2B
|
||
|
||
; TCCR2A - Timer/Counter2 Control Register A
|
||
.equ WGM20 = 0 ; Waveform Genration Mode
|
||
.equ WGM21 = 1 ; Waveform Genration Mode
|
||
.equ COM2B0 = 4 ; Compare Output Mode bit 0
|
||
.equ COM2B1 = 5 ; Compare Output Mode bit 1
|
||
.equ COM2A0 = 6 ; Compare Output Mode bit 1
|
||
.equ COM2A1 = 7 ; Compare Output Mode bit 1
|
||
|
||
; TCCR2B - Timer/Counter2 Control Register B
|
||
.equ CS20 = 0 ; Clock Select bit 0
|
||
.equ CS21 = 1 ; Clock Select bit 1
|
||
.equ CS22 = 2 ; Clock Select bit 2
|
||
.equ WGM22 = 3 ; Waveform Generation Mode
|
||
.equ FOC2B = 6 ; Force Output Compare B
|
||
.equ FOC2A = 7 ; Force Output Compare A
|
||
|
||
; TCNT2 - Timer/Counter2
|
||
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
|
||
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
|
||
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
|
||
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
|
||
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
|
||
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
|
||
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
|
||
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
|
||
|
||
; OCR2A - Timer/Counter2 Output Compare Register A
|
||
.equ OCR2A_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
|
||
.equ OCR2A_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
|
||
.equ OCR2A_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
|
||
.equ OCR2A_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
|
||
.equ OCR2A_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
|
||
.equ OCR2A_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
|
||
.equ OCR2A_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
|
||
.equ OCR2A_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
|
||
|
||
; OCR2B - Timer/Counter2 Output Compare Register B
|
||
.equ OCR2B_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
|
||
.equ OCR2B_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
|
||
.equ OCR2B_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
|
||
.equ OCR2B_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
|
||
.equ OCR2B_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
|
||
.equ OCR2B_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
|
||
.equ OCR2B_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
|
||
.equ OCR2B_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
|
||
|
||
; ASSR - Asynchronous Status Register
|
||
.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy
|
||
.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy
|
||
.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy
|
||
.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy
|
||
.equ TCN2UB = 4 ; Timer/Counter2 Update Busy
|
||
.equ AS2 = 5 ; Asynchronous Timer/Counter2
|
||
.equ EXCLK = 6 ; Enable External Clock Input
|
||
|
||
; GTCCR - General Timer Counter Control register
|
||
.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2
|
||
.equ PSR2 = PSRASY ; For compatibility
|
||
;.equ TSM = 7 ; Timer/Counter Synchronization Mode
|
||
|
||
|
||
; ***** AD_CONVERTER *****************
|
||
; ADMUX - The ADC multiplexer Selection Register
|
||
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
|
||
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
|
||
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
|
||
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
|
||
.equ ADLAR = 5 ; Left Adjust Result
|
||
.equ REFS0 = 6 ; Reference Selection Bit 0
|
||
.equ REFS1 = 7 ; Reference Selection Bit 1
|
||
|
||
; ADCSRA - The ADC Control and Status register A
|
||
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
|
||
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
|
||
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
|
||
.equ ADIE = 3 ; ADC Interrupt Enable
|
||
.equ ADIF = 4 ; ADC Interrupt Flag
|
||
.equ ADATE = 5 ; ADC Auto Trigger Enable
|
||
.equ ADSC = 6 ; ADC Start Conversion
|
||
.equ ADEN = 7 ; ADC Enable
|
||
|
||
; ADCSRB - The ADC Control and Status register B
|
||
.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0
|
||
.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1
|
||
.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2
|
||
.equ ACME = 6 ;
|
||
|
||
; ADCH - ADC Data Register High Byte
|
||
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
|
||
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
|
||
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
|
||
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
|
||
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
|
||
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
|
||
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
|
||
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
|
||
|
||
; ADCL - ADC Data Register Low Byte
|
||
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
|
||
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
|
||
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
|
||
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
|
||
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
|
||
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
|
||
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
|
||
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
|
||
|
||
; DIDR0 - Digital Input Disable Register
|
||
.equ ADC0D = 0 ;
|
||
.equ ADC1D = 1 ;
|
||
.equ ADC2D = 2 ;
|
||
.equ ADC3D = 3 ;
|
||
.equ ADC4D = 4 ;
|
||
.equ ADC5D = 5 ;
|
||
|
||
|
||
; ***** ANALOG_COMPARATOR ************
|
||
; ACSR - Analog Comparator Control And Status Register
|
||
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
|
||
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
|
||
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
|
||
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
|
||
.equ ACI = 4 ; Analog Comparator Interrupt Flag
|
||
.equ ACO = 5 ; Analog Compare Output
|
||
.equ ACBG = 6 ; Analog Comparator Bandgap Select
|
||
.equ ACD = 7 ; Analog Comparator Disable
|
||
|
||
; DIDR1 - Digital Input Disable Register 1
|
||
.equ AIN0D = 0 ; AIN0 Digital Input Disable
|
||
.equ AIN1D = 1 ; AIN1 Digital Input Disable
|
||
|
||
|
||
; ***** PORTB ************************
|
||
; PORTB - Port B Data Register
|
||
.equ PORTB0 = 0 ; Port B Data Register bit 0
|
||
.equ PB0 = 0 ; For compatibility
|
||
.equ PORTB1 = 1 ; Port B Data Register bit 1
|
||
.equ PB1 = 1 ; For compatibility
|
||
.equ PORTB2 = 2 ; Port B Data Register bit 2
|
||
.equ PB2 = 2 ; For compatibility
|
||
.equ PORTB3 = 3 ; Port B Data Register bit 3
|
||
.equ PB3 = 3 ; For compatibility
|
||
.equ PORTB4 = 4 ; Port B Data Register bit 4
|
||
.equ PB4 = 4 ; For compatibility
|
||
.equ PORTB5 = 5 ; Port B Data Register bit 5
|
||
.equ PB5 = 5 ; For compatibility
|
||
.equ PORTB6 = 6 ; Port B Data Register bit 6
|
||
.equ PB6 = 6 ; For compatibility
|
||
.equ PORTB7 = 7 ; Port B Data Register bit 7
|
||
.equ PB7 = 7 ; For compatibility
|
||
|
||
; DDRB - Port B Data Direction Register
|
||
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
|
||
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
|
||
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
|
||
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
|
||
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
|
||
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
|
||
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
|
||
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
|
||
|
||
; PINB - Port B Input Pins
|
||
.equ PINB0 = 0 ; Port B Input Pins bit 0
|
||
.equ PINB1 = 1 ; Port B Input Pins bit 1
|
||
.equ PINB2 = 2 ; Port B Input Pins bit 2
|
||
.equ PINB3 = 3 ; Port B Input Pins bit 3
|
||
.equ PINB4 = 4 ; Port B Input Pins bit 4
|
||
.equ PINB5 = 5 ; Port B Input Pins bit 5
|
||
.equ PINB6 = 6 ; Port B Input Pins bit 6
|
||
.equ PINB7 = 7 ; Port B Input Pins bit 7
|
||
|
||
|
||
; ***** PORTC ************************
|
||
; PORTC - Port C Data Register
|
||
.equ PORTC0 = 0 ; Port C Data Register bit 0
|
||
.equ PC0 = 0 ; For compatibility
|
||
.equ PORTC1 = 1 ; Port C Data Register bit 1
|
||
.equ PC1 = 1 ; For compatibility
|
||
.equ PORTC2 = 2 ; Port C Data Register bit 2
|
||
.equ PC2 = 2 ; For compatibility
|
||
.equ PORTC3 = 3 ; Port C Data Register bit 3
|
||
.equ PC3 = 3 ; For compatibility
|
||
.equ PORTC4 = 4 ; Port C Data Register bit 4
|
||
.equ PC4 = 4 ; For compatibility
|
||
.equ PORTC5 = 5 ; Port C Data Register bit 5
|
||
.equ PC5 = 5 ; For compatibility
|
||
.equ PORTC6 = 6 ; Port C Data Register bit 6
|
||
.equ PC6 = 6 ; For compatibility
|
||
|
||
; DDRC - Port C Data Direction Register
|
||
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
|
||
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
|
||
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
|
||
.equ DDC3 = 3 ; Port C Data Direction Register bit 3
|
||
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
|
||
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
|
||
.equ DDC6 = 6 ; Port C Data Direction Register bit 6
|
||
|
||
; PINC - Port C Input Pins
|
||
.equ PINC0 = 0 ; Port C Input Pins bit 0
|
||
.equ PINC1 = 1 ; Port C Input Pins bit 1
|
||
.equ PINC2 = 2 ; Port C Input Pins bit 2
|
||
.equ PINC3 = 3 ; Port C Input Pins bit 3
|
||
.equ PINC4 = 4 ; Port C Input Pins bit 4
|
||
.equ PINC5 = 5 ; Port C Input Pins bit 5
|
||
.equ PINC6 = 6 ; Port C Input Pins bit 6
|
||
|
||
|
||
; ***** PORTD ************************
|
||
; PORTD - Port D Data Register
|
||
.equ PORTD0 = 0 ; Port D Data Register bit 0
|
||
.equ PD0 = 0 ; For compatibility
|
||
.equ PORTD1 = 1 ; Port D Data Register bit 1
|
||
.equ PD1 = 1 ; For compatibility
|
||
.equ PORTD2 = 2 ; Port D Data Register bit 2
|
||
.equ PD2 = 2 ; For compatibility
|
||
.equ PORTD3 = 3 ; Port D Data Register bit 3
|
||
.equ PD3 = 3 ; For compatibility
|
||
.equ PORTD4 = 4 ; Port D Data Register bit 4
|
||
.equ PD4 = 4 ; For compatibility
|
||
.equ PORTD5 = 5 ; Port D Data Register bit 5
|
||
.equ PD5 = 5 ; For compatibility
|
||
.equ PORTD6 = 6 ; Port D Data Register bit 6
|
||
.equ PD6 = 6 ; For compatibility
|
||
.equ PORTD7 = 7 ; Port D Data Register bit 7
|
||
.equ PD7 = 7 ; For compatibility
|
||
|
||
; DDRD - Port D Data Direction Register
|
||
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
|
||
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
|
||
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
|
||
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
|
||
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
|
||
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
|
||
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
|
||
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
|
||
|
||
; PIND - Port D Input Pins
|
||
.equ PIND0 = 0 ; Port D Input Pins bit 0
|
||
.equ PIND1 = 1 ; Port D Input Pins bit 1
|
||
.equ PIND2 = 2 ; Port D Input Pins bit 2
|
||
.equ PIND3 = 3 ; Port D Input Pins bit 3
|
||
.equ PIND4 = 4 ; Port D Input Pins bit 4
|
||
.equ PIND5 = 5 ; Port D Input Pins bit 5
|
||
.equ PIND6 = 6 ; Port D Input Pins bit 6
|
||
.equ PIND7 = 7 ; Port D Input Pins bit 7
|
||
|
||
|
||
; ***** TIMER_COUNTER_0 **************
|
||
; TIMSK0 - Timer/Counter0 Interrupt Mask Register
|
||
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
|
||
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
|
||
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
|
||
|
||
; TIFR0 - Timer/Counter0 Interrupt Flag register
|
||
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
|
||
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A
|
||
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
|
||
|
||
; TCCR0A - Timer/Counter Control Register A
|
||
.equ WGM00 = 0 ; Waveform Generation Mode
|
||
.equ WGM01 = 1 ; Waveform Generation Mode
|
||
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm
|
||
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm
|
||
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode
|
||
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode
|
||
|
||
; TCCR0B - Timer/Counter Control Register B
|
||
.equ CS00 = 0 ; Clock Select
|
||
.equ CS01 = 1 ; Clock Select
|
||
.equ CS02 = 2 ; Clock Select
|
||
.equ WGM02 = 3 ;
|
||
.equ FOC0B = 6 ; Force Output Compare B
|
||
.equ FOC0A = 7 ; Force Output Compare A
|
||
|
||
; TCNT0 - Timer/Counter0
|
||
.equ TCNT0_0 = 0 ;
|
||
.equ TCNT0_1 = 1 ;
|
||
.equ TCNT0_2 = 2 ;
|
||
.equ TCNT0_3 = 3 ;
|
||
.equ TCNT0_4 = 4 ;
|
||
.equ TCNT0_5 = 5 ;
|
||
.equ TCNT0_6 = 6 ;
|
||
.equ TCNT0_7 = 7 ;
|
||
|
||
; OCR0A - Timer/Counter0 Output Compare Register
|
||
.equ OCR0A_0 = 0 ;
|
||
.equ OCR0A_1 = 1 ;
|
||
.equ OCR0A_2 = 2 ;
|
||
.equ OCR0A_3 = 3 ;
|
||
.equ OCR0A_4 = 4 ;
|
||
.equ OCR0A_5 = 5 ;
|
||
.equ OCR0A_6 = 6 ;
|
||
.equ OCR0A_7 = 7 ;
|
||
|
||
; OCR0B - Timer/Counter0 Output Compare Register
|
||
.equ OCR0B_0 = 0 ;
|
||
.equ OCR0B_1 = 1 ;
|
||
.equ OCR0B_2 = 2 ;
|
||
.equ OCR0B_3 = 3 ;
|
||
.equ OCR0B_4 = 4 ;
|
||
.equ OCR0B_5 = 5 ;
|
||
.equ OCR0B_6 = 6 ;
|
||
.equ OCR0B_7 = 7 ;
|
||
|
||
; GTCCR - General Timer/Counter Control Register
|
||
;.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
.equ PSR10 = PSRSYNC ; For compatibility
|
||
;.equ TSM = 7 ; Timer/Counter Synchronization Mode
|
||
|
||
|
||
; ***** EXTERNAL_INTERRUPT ***********
|
||
; EICRA - External Interrupt Control Register
|
||
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0
|
||
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1
|
||
.equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0
|
||
.equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1
|
||
|
||
; EIMSK - External Interrupt Mask Register
|
||
.equ INT0 = 0 ; External Interrupt Request 0 Enable
|
||
.equ INT1 = 1 ; External Interrupt Request 1 Enable
|
||
|
||
; EIFR - External Interrupt Flag Register
|
||
.equ INTF0 = 0 ; External Interrupt Flag 0
|
||
.equ INTF1 = 1 ; External Interrupt Flag 1
|
||
|
||
; PCICR - Pin Change Interrupt Control Register
|
||
.equ PCIE0 = 0 ; Pin Change Interrupt Enable 0
|
||
.equ PCIE1 = 1 ; Pin Change Interrupt Enable 1
|
||
.equ PCIE2 = 2 ; Pin Change Interrupt Enable 2
|
||
|
||
; PCMSK2 - Pin Change Mask Register 2
|
||
.equ PCINT16 = 0 ; Pin Change Enable Mask 16
|
||
.equ PCINT17 = 1 ; Pin Change Enable Mask 17
|
||
.equ PCINT18 = 2 ; Pin Change Enable Mask 18
|
||
.equ PCINT19 = 3 ; Pin Change Enable Mask 19
|
||
.equ PCINT20 = 4 ; Pin Change Enable Mask 20
|
||
.equ PCINT21 = 5 ; Pin Change Enable Mask 21
|
||
.equ PCINT22 = 6 ; Pin Change Enable Mask 22
|
||
.equ PCINT23 = 7 ; Pin Change Enable Mask 23
|
||
|
||
; PCMSK1 - Pin Change Mask Register 1
|
||
.equ PCINT8 = 0 ; Pin Change Enable Mask 8
|
||
.equ PCINT9 = 1 ; Pin Change Enable Mask 9
|
||
.equ PCINT10 = 2 ; Pin Change Enable Mask 10
|
||
.equ PCINT11 = 3 ; Pin Change Enable Mask 11
|
||
.equ PCINT12 = 4 ; Pin Change Enable Mask 12
|
||
.equ PCINT13 = 5 ; Pin Change Enable Mask 13
|
||
.equ PCINT14 = 6 ; Pin Change Enable Mask 14
|
||
|
||
; PCMSK0 - Pin Change Mask Register 0
|
||
.equ PCINT0 = 0 ; Pin Change Enable Mask 0
|
||
.equ PCINT1 = 1 ; Pin Change Enable Mask 1
|
||
.equ PCINT2 = 2 ; Pin Change Enable Mask 2
|
||
.equ PCINT3 = 3 ; Pin Change Enable Mask 3
|
||
.equ PCINT4 = 4 ; Pin Change Enable Mask 4
|
||
.equ PCINT5 = 5 ; Pin Change Enable Mask 5
|
||
.equ PCINT6 = 6 ; Pin Change Enable Mask 6
|
||
.equ PCINT7 = 7 ; Pin Change Enable Mask 7
|
||
|
||
; PCIFR - Pin Change Interrupt Flag Register
|
||
.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0
|
||
.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1
|
||
.equ PCIF2 = 2 ; Pin Change Interrupt Flag 2
|
||
|
||
|
||
; ***** SPI **************************
|
||
; SPDR - SPI Data Register
|
||
.equ SPDR0 = 0 ; SPI Data Register bit 0
|
||
.equ SPDR1 = 1 ; SPI Data Register bit 1
|
||
.equ SPDR2 = 2 ; SPI Data Register bit 2
|
||
.equ SPDR3 = 3 ; SPI Data Register bit 3
|
||
.equ SPDR4 = 4 ; SPI Data Register bit 4
|
||
.equ SPDR5 = 5 ; SPI Data Register bit 5
|
||
.equ SPDR6 = 6 ; SPI Data Register bit 6
|
||
.equ SPDR7 = 7 ; SPI Data Register bit 7
|
||
|
||
; SPSR - SPI Status Register
|
||
.equ SPI2X = 0 ; Double SPI Speed Bit
|
||
.equ WCOL = 6 ; Write Collision Flag
|
||
.equ SPIF = 7 ; SPI Interrupt Flag
|
||
|
||
; SPCR - SPI Control Register
|
||
.equ SPR0 = 0 ; SPI Clock Rate Select 0
|
||
.equ SPR1 = 1 ; SPI Clock Rate Select 1
|
||
.equ CPHA = 2 ; Clock Phase
|
||
.equ CPOL = 3 ; Clock polarity
|
||
.equ MSTR = 4 ; Master/Slave Select
|
||
.equ DORD = 5 ; Data Order
|
||
.equ SPE = 6 ; SPI Enable
|
||
.equ SPIE = 7 ; SPI Interrupt Enable
|
||
|
||
|
||
; ***** WATCHDOG *********************
|
||
; WDTCSR - Watchdog Timer Control Register
|
||
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
|
||
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
|
||
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
|
||
.equ WDE = 3 ; Watch Dog Enable
|
||
.equ WDCE = 4 ; Watchdog Change Enable
|
||
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
|
||
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
|
||
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
|
||
|
||
|
||
; ***** CPU **************************
|
||
; SREG - Status Register
|
||
.equ SREG_C = 0 ; Carry Flag
|
||
.equ SREG_Z = 1 ; Zero Flag
|
||
.equ SREG_N = 2 ; Negative Flag
|
||
.equ SREG_V = 3 ; Two's Complement Overflow Flag
|
||
.equ SREG_S = 4 ; Sign Bit
|
||
.equ SREG_H = 5 ; Half Carry Flag
|
||
.equ SREG_T = 6 ; Bit Copy Storage
|
||
.equ SREG_I = 7 ; Global Interrupt Enable
|
||
|
||
; OSCCAL - Oscillator Calibration Value
|
||
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
|
||
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
|
||
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
|
||
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
|
||
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
|
||
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
|
||
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
|
||
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7
|
||
|
||
; CLKPR - Clock Prescale Register
|
||
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
|
||
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
|
||
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
|
||
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
|
||
.equ CLKPCE = 7 ; Clock Prescaler Change Enable
|
||
|
||
; SPMCSR - Store Program Memory Control and Status Register
|
||
.equ SELFPRGEN = 0; Added for backwards compatibility
|
||
.equ SPMEN = 0 ; Store Program Memory
|
||
.equ PGERS = 1 ; Page Erase
|
||
.equ PGWRT = 2 ; Page Write
|
||
.equ BLBSET = 3 ; Boot Lock Bit Set
|
||
.equ RWWSRE = 4 ; Read-While-Write section read enable
|
||
.equ SIGRD = 5 ; Signature Row Read
|
||
.equ RWWSB = 6 ; Read-While-Write Section Busy
|
||
.equ SPMIE = 7 ; SPM Interrupt Enable
|
||
|
||
; MCUCR - MCU Control Register
|
||
.equ IVCE = 0 ;
|
||
.equ IVSEL = 1 ;
|
||
.equ PUD = 4 ;
|
||
.equ BODSE = 5 ; BOD Sleep Enable
|
||
.equ BODS = 6 ; BOD Sleep
|
||
|
||
; MCUSR - MCU Status Register
|
||
.equ PORF = 0 ; Power-on reset flag
|
||
.equ EXTRF = 1 ; External Reset Flag
|
||
.equ EXTREF = EXTRF ; For compatibility
|
||
.equ BORF = 2 ; Brown-out Reset Flag
|
||
.equ WDRF = 3 ; Watchdog Reset Flag
|
||
|
||
; SMCR - Sleep Mode Control Register
|
||
.equ SE = 0 ; Sleep Enable
|
||
.equ SM0 = 1 ; Sleep Mode Select Bit 0
|
||
.equ SM1 = 2 ; Sleep Mode Select Bit 1
|
||
.equ SM2 = 3 ; Sleep Mode Select Bit 2
|
||
|
||
; GPIOR2 - General Purpose I/O Register 2
|
||
.equ GPIOR20 = 0 ;
|
||
.equ GPIOR21 = 1 ;
|
||
.equ GPIOR22 = 2 ;
|
||
.equ GPIOR23 = 3 ;
|
||
.equ GPIOR24 = 4 ;
|
||
.equ GPIOR25 = 5 ;
|
||
.equ GPIOR26 = 6 ;
|
||
.equ GPIOR27 = 7 ;
|
||
|
||
; GPIOR1 - General Purpose I/O Register 1
|
||
.equ GPIOR10 = 0 ;
|
||
.equ GPIOR11 = 1 ;
|
||
.equ GPIOR12 = 2 ;
|
||
.equ GPIOR13 = 3 ;
|
||
.equ GPIOR14 = 4 ;
|
||
.equ GPIOR15 = 5 ;
|
||
.equ GPIOR16 = 6 ;
|
||
.equ GPIOR17 = 7 ;
|
||
|
||
; GPIOR0 - General Purpose I/O Register 0
|
||
.equ GPIOR00 = 0 ;
|
||
.equ GPIOR01 = 1 ;
|
||
.equ GPIOR02 = 2 ;
|
||
.equ GPIOR03 = 3 ;
|
||
.equ GPIOR04 = 4 ;
|
||
.equ GPIOR05 = 5 ;
|
||
.equ GPIOR06 = 6 ;
|
||
.equ GPIOR07 = 7 ;
|
||
|
||
; PRR - Power Reduction Register
|
||
.equ PRADC = 0 ; Power Reduction ADC
|
||
.equ PRUSART0 = 1 ; Power Reduction USART
|
||
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface
|
||
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1
|
||
.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0
|
||
.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2
|
||
.equ PRTWI = 7 ; Power Reduction TWI
|
||
|
||
|
||
; ***** EEPROM ***********************
|
||
; EEARL - EEPROM Address Register Low Byte
|
||
.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0
|
||
.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1
|
||
.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2
|
||
.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3
|
||
.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4
|
||
.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5
|
||
.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6
|
||
.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7
|
||
|
||
; EEARH - EEPROM Address Register High Byte
|
||
.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 8
|
||
.equ EEAR9 = 1 ; EEPROM Read/Write Access Bit 9
|
||
|
||
; EEDR - EEPROM Data Register
|
||
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
|
||
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
|
||
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
|
||
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
|
||
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
|
||
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
|
||
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
|
||
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
|
||
|
||
; EECR - EEPROM Control Register
|
||
.equ EERE = 0 ; EEPROM Read Enable
|
||
.equ EEPE = 1 ; EEPROM Write Enable
|
||
.equ EEMPE = 2 ; EEPROM Master Write Enable
|
||
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
|
||
.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0
|
||
.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1
|
||
|
||
|
||
|
||
; ***** LOCKSBITS ********************************************************
|
||
.equ LB1 = 0 ; Lock bit
|
||
.equ LB2 = 1 ; Lock bit
|
||
.equ BLB01 = 2 ; Boot Lock bit
|
||
.equ BLB02 = 3 ; Boot Lock bit
|
||
.equ BLB11 = 4 ; Boot lock bit
|
||
.equ BLB12 = 5 ; Boot lock bit
|
||
|
||
|
||
; ***** FUSES ************************************************************
|
||
; LOW fuse bits
|
||
.equ CKSEL0 = 0 ; Select Clock Source
|
||
.equ CKSEL1 = 1 ; Select Clock Source
|
||
.equ CKSEL2 = 2 ; Select Clock Source
|
||
.equ CKSEL3 = 3 ; Select Clock Source
|
||
.equ SUT0 = 4 ; Select start-up time
|
||
.equ SUT1 = 5 ; Select start-up time
|
||
.equ CKOUT = 6 ; Clock output
|
||
.equ CKDIV8 = 7 ; Divide clock by 8
|
||
|
||
; HIGH fuse bits
|
||
.equ BOOTRST = 0 ; Select reset vector
|
||
.equ BOOTSZ0 = 1 ; Select boot size
|
||
.equ BOOTSZ1 = 2 ; Select boot size
|
||
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
|
||
.equ WDTON = 4 ; Watchdog Timer Always On
|
||
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
|
||
.equ DWEN = 6 ; debugWIRE Enable
|
||
.equ RSTDISBL = 7 ; External reset disable
|
||
|
||
; EXTENDED fuse bits
|
||
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level
|
||
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level
|
||
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level
|
||
|
||
|
||
|
||
; ***** CPU REGISTER DEFINITIONS *****************************************
|
||
.def XH = r27
|
||
.def XL = r26
|
||
.def YH = r29
|
||
.def YL = r28
|
||
.def ZH = r31
|
||
.def ZL = r30
|
||
|
||
|
||
|
||
; ***** DATA MEMORY DECLARATIONS *****************************************
|
||
.equ FLASHEND = 0x3fff ; Note: Word address
|
||
.equ IOEND = 0x00ff
|
||
.equ SRAM_START = 0x0100
|
||
.equ SRAM_SIZE = 2048
|
||
.equ RAMEND = 0x08ff
|
||
.equ XRAMEND = 0x0000
|
||
.equ E2END = 0x03ff
|
||
.equ EEPROMEND = 0x03ff
|
||
.equ EEADRBITS = 10
|
||
#pragma AVRPART MEMORY PROG_FLASH 32768
|
||
#pragma AVRPART MEMORY EEPROM 1024
|
||
#pragma AVRPART MEMORY INT_SRAM SIZE 2048
|
||
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
|
||
|
||
|
||
|
||
; ***** BOOTLOADER DECLARATIONS ******************************************
|
||
.equ NRWW_START_ADDR = 0x3800
|
||
.equ NRWW_STOP_ADDR = 0x3fff
|
||
.equ RWW_START_ADDR = 0x0
|
||
.equ RWW_STOP_ADDR = 0x37ff
|
||
.equ PAGESIZE = 64
|
||
.equ FIRSTBOOTSTART = 0x3f00
|
||
.equ SECONDBOOTSTART = 0x3e00
|
||
.equ THIRDBOOTSTART = 0x3c00
|
||
.equ FOURTHBOOTSTART = 0x3800
|
||
.equ SMALLBOOTSTART = FIRSTBOOTSTART
|
||
.equ LARGEBOOTSTART = FOURTHBOOTSTART
|
||
|
||
|
||
|
||
; ***** INTERRUPT VECTORS ************************************************
|
||
.equ INT0addr = 0x0002 ; External Interrupt Request 0
|
||
.equ INT1addr = 0x0004 ; External Interrupt Request 1
|
||
.equ PCI0addr = 0x0006 ; Pin Change Interrupt Request 0
|
||
.equ PCI1addr = 0x0008 ; Pin Change Interrupt Request 0
|
||
.equ PCI2addr = 0x000a ; Pin Change Interrupt Request 1
|
||
.equ WDTaddr = 0x000c ; Watchdog Time-out Interrupt
|
||
.equ OC2Aaddr = 0x000e ; Timer/Counter2 Compare Match A
|
||
.equ OC2Baddr = 0x0010 ; Timer/Counter2 Compare Match A
|
||
.equ OVF2addr = 0x0012 ; Timer/Counter2 Overflow
|
||
.equ ICP1addr = 0x0014 ; Timer/Counter1 Capture Event
|
||
.equ OC1Aaddr = 0x0016 ; Timer/Counter1 Compare Match A
|
||
.equ OC1Baddr = 0x0018 ; Timer/Counter1 Compare Match B
|
||
.equ OVF1addr = 0x001a ; Timer/Counter1 Overflow
|
||
.equ OC0Aaddr = 0x001c ; TimerCounter0 Compare Match A
|
||
.equ OC0Baddr = 0x001e ; TimerCounter0 Compare Match B
|
||
.equ OVF0addr = 0x0020 ; Timer/Couner0 Overflow
|
||
.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete
|
||
.equ URXCaddr = 0x0024 ; USART Rx Complete
|
||
.equ UDREaddr = 0x0026 ; USART, Data Register Empty
|
||
.equ UTXCaddr = 0x0028 ; USART Tx Complete
|
||
.equ ADCCaddr = 0x002a ; ADC Conversion Complete
|
||
.equ ERDYaddr = 0x002c ; EEPROM Ready
|
||
.equ ACIaddr = 0x002e ; Analog Comparator
|
||
.equ TWIaddr = 0x0030 ; Two-wire Serial Interface
|
||
.equ SPMRaddr = 0x0032 ; Store Program Memory Read
|
||
|
||
.equ INT_VECTORS_SIZE = 52 ; size in words
|
||
|
||
#endif /* _M328PDEF_INC_ */
|
||
|
||
; ***** END OF FILE ******************************************************
|
||
|
||
; iButton serial number reader
|
||
; Addapter pour lire le 18b20 par http://adriy.be
|
||
; http://avr-mcu.dxp.pl
|
||
; e-mail: radek(at)dxp.pl
|
||
; (c) Radoslaw Kwiecien
|
||
;------------------------------------------------------------------------------
|
||
|
||
;------------------------------------------------------------------------------
|
||
; Defines
|
||
;------------------------------------------------------------------------------
|
||
#define F_CPU 16000000
|
||
|
||
;Table 3. DS18B20 Function Command Set p12
|
||
#define ReadRom 0x33
|
||
#define SkipRom 0xcc
|
||
#define ConvertTemp 0x44 ; Initiates temperature conversion.
|
||
#define WScratch 0x4e ; Writes data into scratchpad bytes 2, 3, and4 (TH, TL, and configuration registers).
|
||
#define RScratch 0xbe ; Reads the entire scratchpad including theCRC byte.
|
||
;------------------------------------------------------------------------------
|
||
; Data segment, variable definitions
|
||
;------------------------------------------------------------------------------
|
||
.dseg
|
||
|
||
000100 SerialNumber: .byte 8
|
||
|
||
;------------------------------------------------------------------------------
|
||
; Code segment
|
||
;------------------------------------------------------------------------------
|
||
.cseg
|
||
;------------------------------------------------------------------------------
|
||
; Include required files
|
||
;------------------------------------------------------------------------------
|
||
#include "vectors.asm"
|
||
|
||
.org 0 ; Reset
|
||
000000 c168 rjmp ProgramEntryPoint
|
||
.org INT0addr
|
||
000002 9518 reti
|
||
.org INT1addr
|
||
000004 9518 reti
|
||
.org PCI0addr
|
||
000006 9518 reti
|
||
.org PCI1addr
|
||
000008 9518 reti
|
||
.org PCI2addr
|
||
00000a 9518 reti
|
||
.org WDTaddr
|
||
00000c 9518 reti
|
||
.org OC2Aaddr
|
||
00000e 9518 reti
|
||
.org OC2Baddr
|
||
000010 9518 reti
|
||
.org OVF2addr
|
||
000012 9518 reti
|
||
.org ICP1addr
|
||
000014 9518 reti
|
||
.org OC1Aaddr
|
||
000016 9518 reti
|
||
.org OC1Baddr
|
||
000018 9518 reti
|
||
.org OVF1addr
|
||
00001a 9518 reti
|
||
.org OC0Aaddr
|
||
00001c 9518 reti
|
||
.org OC0Baddr
|
||
00001e 9518 reti
|
||
.org OVF0addr
|
||
000020 9518 reti
|
||
.org SPIaddr
|
||
000022 9518 reti
|
||
.org URXCaddr
|
||
000024 9518 reti
|
||
.org UDREaddr
|
||
000026 9518 reti
|
||
.org UTXCaddr
|
||
000028 9518 reti
|
||
.org ADCCaddr
|
||
00002a 9518 reti
|
||
.org ERDYaddr
|
||
00002c 9518 reti
|
||
.org ACIaddr
|
||
00002e 9518 reti
|
||
.org TWIaddr
|
||
000030 9518 reti
|
||
.org SPMRaddr
|
||
000032 9518 reti
|
||
|
||
|
||
|
||
; .org INT0addr ; External Interrupt Request 0
|
||
; reti
|
||
; .org INT1addr ; External Interrupt Request 1
|
||
; reti
|
||
; .org ICP1addr ; Timer/Counter1 Capture Event
|
||
; reti
|
||
; .org OC1Aaddr ; Timer/Counter1 Compare Match A
|
||
; reti
|
||
; .org OVF1addr ; Timer/Counter1 Overflow
|
||
; reti
|
||
; .org OVF0addr ; Timer/Counter0 Overflow
|
||
; reti
|
||
; .org URXCaddr ; USART, Rx Complete
|
||
; reti
|
||
; .org UDREaddr ; USART Data Register Empty
|
||
; reti
|
||
; .org UTXCaddr ; USART, Tx Complete
|
||
; reti
|
||
; .org ACIaddr ; Analog Comparator
|
||
; reti
|
||
; .org PCIaddr ;
|
||
; reti
|
||
; .org OC1Baddr ;
|
||
; reti
|
||
; .org OC0Aaddr ;
|
||
; reti
|
||
; .org OC0Baddr ;
|
||
; reti
|
||
; .org USI_STARTaddr ; USI Start Condition
|
||
; reti
|
||
; .org USI_OVFaddr ; USI Overflow
|
||
; reti
|
||
; .org ERDYaddr ;
|
||
; reti
|
||
; .org WDTaddr ; Watchdog Timer Overflow
|
||
; reti
|
||
#include "hd44780.asm"
|
||
|
||
; HD44780 LCD Assembly driver
|
||
; http://avr-mcu.dxp.pl
|
||
; e-mail : radek@dxp.pl
|
||
; (c) Radoslaw Kwiecien
|
||
;------------------------------------------------------------------------------
|
||
.include "hd44780.inc"
|
||
|
||
|
||
#define HD44780_HOME 0x02
|
||
|
||
#define HD44780_ENTRY_MODE 0x04
|
||
#define HD44780_EM_SHIFT_CURSOR 0
|
||
#define HD44780_EM_SHIFT_DISPLAY 1
|
||
#define HD44780_EM_DECREMENT 0
|
||
#define HD44780_EM_INCREMENT 2
|
||
|
||
#define HD44780_DISPLAY_ONOFF 0x08
|
||
#define HD44780_DISPLAY_OFF 0
|
||
#define HD44780_DISPLAY_ON 4
|
||
#define HD44780_CURSOR_OFF 0
|
||
#define HD44780_CURSOR_ON 2
|
||
#define HD44780_CURSOR_NOBLINK 0
|
||
#define HD44780_CURSOR_BLINK 1
|
||
|
||
#define HD44780_DISPLAY_CURSOR_SHIFT 0x10
|
||
#define HD44780_SHIFT_CURSOR 0
|
||
#define HD44780_SHIFT_DISPLAY 8
|
||
#define HD44780_SHIFT_LEFT 0
|
||
#define HD44780_SHIFT_RIGHT 4
|
||
|
||
#define HD44780_FUNCTION_SET 0x20
|
||
#define HD44780_FONT5x7 0
|
||
#define HD44780_FONT5x10 4
|
||
#define HD44780_ONE_LINE 0
|
||
#define HD44780_TWO_LINE 8
|
||
#define HD44780_4_BIT 0
|
||
#define HD44780_8_BIT 16
|
||
|
||
#define HD44780_CGRAM_SET 0x40
|
||
|
||
#define HD44780_DDRAM_SET 0x80
|
||
|
||
#define HD44780_LINE0 0x00
|
||
#define HD44780_LINE1 0x40
|
||
|
||
.equ LCD_PORT = PORTD
|
||
.equ LCD_DDR = DDRD
|
||
.equ LCD_PIN = PIND
|
||
|
||
.equ LCD_D4 = 5
|
||
.equ LCD_D5 = 4
|
||
.equ LCD_D6 = 3
|
||
.equ LCD_D7 = 2
|
||
|
||
.equ LCD_RS = 6
|
||
.equ LCD_EN = 7
|
||
|
||
;------------------------------------------------------------------------------
|
||
; Data segment
|
||
;------------------------------------------------------------------------------
|
||
.dseg
|
||
;------------------------------------------------------------------------------
|
||
; Code segment
|
||
;------------------------------------------------------------------------------
|
||
.cseg
|
||
#include "div8u.asm"
|
||
|
||
;***** Subroutine Register Variables
|
||
|
||
.def drem8u =r15 ;remainder
|
||
.def dres8u =r16 ;result
|
||
.def dd8u =r16 ;dividend
|
||
.def dv8u =r17 ;divisor
|
||
.def dcnt8u =r18 ;loop counter
|
||
|
||
;***** Code
|
||
|
||
div8u:
|
||
000033 18ff sub drem8u,drem8u ; clear remainder and carry
|
||
000034 e029 ldi dcnt8u,9 ; init loop counter
|
||
d8u_1:
|
||
000035 1f00 rol dd8u ; shift left dividend
|
||
000036 952a dec dcnt8u ; decrement counter
|
||
000037 f409 brne d8u_2 ; if done
|
||
000038 9508 ret ; return
|
||
d8u_2:
|
||
000039 1cff rol drem8u ; shift dividend into remainder
|
||
00003a 1af1 sub drem8u,dv8u ; remainder = remainder - divisor
|
||
00003b f418 brcc d8u_3 ; if result negative
|
||
00003c 0ef1 add drem8u,dv8u ; restore remainder
|
||
00003d 9488 clc ; clear carry to be shifted into result
|
||
00003e cff6 rjmp d8u_1 ; else
|
||
d8u_3:
|
||
00003f 9408 sec ; set carry to be shifted into result
|
||
000040 cff4 rjmp d8u_1
|
||
;------------------------------------------------------------------------------
|
||
; Write half byte to LCD
|
||
;------------------------------------------------------------------------------
|
||
LCD_WriteNibble:
|
||
000041 9a5f sbi LCD_PORT, LCD_EN
|
||
|
||
000042 ff00 sbrs r16, 0
|
||
000043 985d cbi LCD_PORT, LCD_D4
|
||
000044 fd00 sbrc r16, 0
|
||
000045 9a5d sbi LCD_PORT, LCD_D4
|
||
|
||
000046 ff01 sbrs r16, 1
|
||
000047 985c cbi LCD_PORT, LCD_D5
|
||
000048 fd01 sbrc r16, 1
|
||
000049 9a5c sbi LCD_PORT, LCD_D5
|
||
|
||
00004a ff02 sbrs r16, 2
|
||
00004b 985b cbi LCD_PORT, LCD_D6
|
||
00004c fd02 sbrc r16, 2
|
||
00004d 9a5b sbi LCD_PORT, LCD_D6
|
||
|
||
00004e ff03 sbrs r16, 3
|
||
00004f 985a cbi LCD_PORT, LCD_D7
|
||
000050 fd03 sbrc r16, 3
|
||
000051 9a5a sbi LCD_PORT, LCD_D7
|
||
|
||
000052 985f cbi LCD_PORT, LCD_EN
|
||
000053 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Write data byte to LCD
|
||
;------------------------------------------------------------------------------
|
||
LCD_WriteData:
|
||
000054 9a5e sbi LCD_PORT, LCD_RS
|
||
000055 930f push r16
|
||
000056 9502 swap r16
|
||
000057 dfe9 rcall LCD_WriteNibble
|
||
000058 910f pop r16
|
||
000059 dfe7 rcall LCD_WriteNibble
|
||
|
||
00005a 27bb clr XH
|
||
00005b efaa ldi XL,250
|
||
00005c d058 rcall Wait4xCycles
|
||
00005d 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Write command byte to LCD
|
||
;------------------------------------------------------------------------------
|
||
LCD_WriteCommand:
|
||
00005e 985e cbi LCD_PORT, LCD_RS
|
||
00005f 930f push r16
|
||
000060 9502 swap r16
|
||
000061 dfdf rcall LCD_WriteNibble
|
||
000062 910f pop r16
|
||
000063 dfdd rcall LCD_WriteNibble
|
||
000064 e002 ldi r16,2
|
||
000065 d052 rcall WaitMiliseconds
|
||
000066 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Write string (from program memory)
|
||
;------------------------------------------------------------------------------
|
||
LCD_WriteString:
|
||
000067 9105 lpm r16, Z+
|
||
000068 3000 cpi r16, 0
|
||
000069 f011 breq exit
|
||
00006a dfe9 rcall LCD_WriteData
|
||
00006b cffb rjmp LCD_WriteString
|
||
exit:
|
||
00006c 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Display one digit in HEX code
|
||
;------------------------------------------------------------------------------
|
||
LCD_WriteHexDigit:
|
||
00006d 300a cpi r16,10
|
||
00006e f020 brlo Num
|
||
00006f e317 ldi r17,'7'
|
||
000070 0f01 add r16,r17
|
||
000071 dfe2 rcall LCD_WriteData
|
||
000072 9508 ret
|
||
Num:
|
||
000073 e310 ldi r17,'0'
|
||
000074 0f01 add r16,r17
|
||
000075 dfde rcall LCD_WriteData
|
||
000076 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Display 8-byte hex value of r16
|
||
;------------------------------------------------------------------------------
|
||
LCD_WriteHex8:
|
||
000077 931f push r17
|
||
000078 930f push r16
|
||
000079 9502 swap r16
|
||
00007a 700f andi r16,0x0F
|
||
00007b dff1 rcall LCD_WriteHexDigit
|
||
|
||
00007c 910f pop r16
|
||
00007d 700f andi r16,0x0F
|
||
00007e dfee rcall LCD_WriteHexDigit
|
||
00007f 911f pop r17
|
||
000080 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Display decimal value of r16
|
||
;------------------------------------------------------------------------------
|
||
LCD_WriteDecimal:
|
||
000081 24ee clr r14
|
||
LCD_WriteDecimalLoop:
|
||
000082 e01a ldi r17,10
|
||
000083 dfaf rcall div8u
|
||
000084 94e3 inc r14
|
||
000085 92ff push r15
|
||
000086 3000 cpi r16,0
|
||
000087 f7d1 brne LCD_WriteDecimalLoop
|
||
|
||
LCD_WriteDecimalLoop2:
|
||
000088 e310 ldi r17,'0'
|
||
000089 910f pop r16
|
||
00008a 0f01 add r16,r17
|
||
00008b dfc8 rcall LCD_WriteData
|
||
00008c 94ea dec r14
|
||
00008d f7d1 brne LCD_WriteDecimalLoop2
|
||
00008e 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Set address in Display Data RAM
|
||
;------------------------------------------------------------------------------
|
||
LCD_SetAddressDD:
|
||
00008f 6800 ori r16, HD44780_DDRAM_SET
|
||
000090 dfcd rcall LCD_WriteCommand
|
||
000091 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Set address in Character Generator RAM
|
||
;------------------------------------------------------------------------------
|
||
LCD_SetAddressCG:
|
||
000092 6400 ori r16, HD44780_CGRAM_SET
|
||
000093 dfca rcall LCD_WriteCommand
|
||
000094 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Initialization of LCD
|
||
;------------------------------------------------------------------------------
|
||
LCD_Init:
|
||
000095 9a55 sbi LCD_DDR, LCD_D4
|
||
000096 9a54 sbi LCD_DDR, LCD_D5
|
||
000097 9a53 sbi LCD_DDR, LCD_D6
|
||
000098 9a52 sbi LCD_DDR, LCD_D7
|
||
|
||
000099 9a56 sbi LCD_DDR, LCD_RS
|
||
00009a 9a57 sbi LCD_DDR, LCD_EN
|
||
|
||
00009b 985e cbi LCD_PORT, LCD_RS
|
||
00009c 985f cbi LCD_PORT, LCD_EN
|
||
|
||
00009d e604 ldi r16, 100
|
||
00009e d019 rcall WaitMiliseconds
|
||
|
||
00009f e013 ldi r17, 3
|
||
InitLoop:
|
||
0000a0 e003 ldi r16, 0x03
|
||
0000a1 df9f rcall LCD_WriteNibble
|
||
0000a2 e005 ldi r16, 5
|
||
0000a3 d014 rcall WaitMiliseconds
|
||
0000a4 951a dec r17
|
||
0000a5 f7d1 brne InitLoop
|
||
|
||
0000a6 e002 ldi r16, 0x02
|
||
0000a7 df99 rcall LCD_WriteNibble
|
||
|
||
0000a8 e001 ldi r16, 1
|
||
0000a9 d00e rcall WaitMiliseconds
|
||
|
||
0000aa e208 ldi r16, HD44780_FUNCTION_SET | HD44780_FONT5x7 | HD44780_TWO_LINE | HD44780_4_BIT
|
||
0000ab dfb2 rcall LCD_WriteCommand
|
||
|
||
0000ac e008 ldi r16, HD44780_DISPLAY_ONOFF | HD44780_DISPLAY_OFF
|
||
0000ad dfb0 rcall LCD_WriteCommand
|
||
|
||
0000ae e001 ldi r16, HD44780_CLEAR
|
||
0000af dfae rcall LCD_WriteCommand
|
||
|
||
0000b0 e006 ldi r16, HD44780_ENTRY_MODE |HD44780_EM_SHIFT_CURSOR | HD44780_EM_INCREMENT
|
||
0000b1 dfac rcall LCD_WriteCommand
|
||
|
||
0000b2 e00c ldi r16, HD44780_DISPLAY_ONOFF | HD44780_DISPLAY_ON | HD44780_CURSOR_OFF | HD44780_CURSOR_NOBLINK
|
||
0000b3 dfaa rcall LCD_WriteCommand
|
||
|
||
0000b4 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; End of file
|
||
;------------------------------------------------------------------------------
|
||
|
||
|
||
#include "wait.asm"
|
||
|
||
; Busy-wait loops utilities module
|
||
; For F_CPU >= 4MHz
|
||
; http://avr-mcu.dxp.pl
|
||
; e-mail : radek@dxp.pl
|
||
; (c) Radoslaw Kwiecien
|
||
;------------------------------------------------------------------------------
|
||
|
||
#ifndef F_CPU
|
||
#endif
|
||
|
||
#if F_CPU < 4000000
|
||
#endif
|
||
|
||
#define CYCLES_PER_US (F_CPU/1000000)
|
||
#define C4PUS (CYCLES_PER_US/4)
|
||
#define DVUS(x) (C4PUS*x)
|
||
|
||
;------------------------------------------------------------------------------
|
||
; Input : XH:XL - number of CPU cycles to wait (divided by four)
|
||
;------------------------------------------------------------------------------
|
||
Wait4xCycles:
|
||
0000b5 9711 sbiw XH:XL, 1 ; x-- (2 cycles)
|
||
0000b6 f7f1 brne Wait4xCycles ; jump if not zero (2 cycles)
|
||
0000b7 9508 ret
|
||
|
||
;------------------------------------------------------------------------------
|
||
; Input : r16 - number of miliseconds to wait
|
||
;------------------------------------------------------------------------------
|
||
WaitMiliseconds:
|
||
0000b8 930f push r16
|
||
WaitMsLoop:
|
||
0000b9 e0b7 ldi XH,HIGH(DVUS(500))
|
||
0000ba eda0 ldi XL,LOW(DVUS(500))
|
||
0000bb dff9 rcall Wait4xCycles
|
||
0000bc e0b7 ldi XH,HIGH(DVUS(500))
|
||
0000bd eda0 ldi XL,LOW(DVUS(500))
|
||
0000be dff6 rcall Wait4xCycles
|
||
0000bf 950a dec r16
|
||
0000c0 f7c1 brne WaitMsLoop
|
||
0000c1 910f pop r16
|
||
0000c2 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
;
|
||
;------------------------------------------------------------------------------
|
||
#include "1-wire.asm"
|
||
|
||
;
|
||
;------------------------------------------------------------------------------
|
||
.equ OW_PORT = PORTB
|
||
.equ OW_PIN = PINB
|
||
.equ OW_DDR = DDRB
|
||
.equ OW_DQ = PB0
|
||
|
||
.def OWCount = r17
|
||
|
||
|
||
|
||
#define ReadRom 0x33
|
||
#define SkipRom 0xcc
|
||
#define ConvertTemp 0x44 ; Initiates temperature conversion.
|
||
#define WScratch 0x4e ; Writes data into scratchpad bytes 2, 3, and4 (TH, TL, and configuration registers).
|
||
#define RScratch 0xbe
|
||
;------------------------------------------------------------------------------
|
||
;
|
||
;------------------------------------------------------------------------------
|
||
|
||
;------------------------------------------------------------------------------
|
||
; Data segment, variable definitions
|
||
;------------------------------------------------------------------------------
|
||
.dseg
|
||
000108 TempWord: .byte 3
|
||
00010b TRegister: .byte 3
|
||
00010e ConfigRegister: .byte 2
|
||
|
||
|
||
|
||
|
||
.cseg
|
||
;------------------------------------------------------------------------------
|
||
; Output : T - presence bit
|
||
;------------------------------------------------------------------------------
|
||
OWReset:
|
||
0000c3 9828 cbi OW_PORT,OW_DQ
|
||
0000c4 9a20 sbi OW_DDR,OW_DQ
|
||
|
||
0000c5 e0b7 ldi XH, HIGH(DVUS(470))
|
||
0000c6 e5a8 ldi XL, LOW(DVUS(470))
|
||
0000c7 dfed rcall Wait4xCycles
|
||
|
||
0000c8 9820 cbi OW_DDR,OW_DQ
|
||
|
||
0000c9 e0b1 ldi XH, HIGH(DVUS(70))
|
||
0000ca e1a8 ldi XL, LOW(DVUS(70))
|
||
0000cb dfe9 rcall Wait4xCycles
|
||
|
||
0000cc 9468 set
|
||
0000cd 9b18 sbis OW_PIN,OW_DQ
|
||
0000ce 94e8 clt
|
||
|
||
0000cf e0b3 ldi XH, HIGH(DVUS(240))
|
||
0000d0 eca0 ldi XL, LOW(DVUS(240))
|
||
0000d1 dfe3 rcall Wait4xCycles
|
||
|
||
0000d2 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Input : C - bit to write
|
||
;------------------------------------------------------------------------------
|
||
OWWriteBit:
|
||
0000d3 f418 brcc OWWriteZero
|
||
0000d4 e0b0 ldi XH, HIGH(DVUS(1))
|
||
0000d5 e0a4 ldi XL, LOW(DVUS(1))
|
||
0000d6 c002 rjmp OWWriteOne
|
||
OWWriteZero:
|
||
0000d7 e0b1 ldi XH, HIGH(DVUS(120))
|
||
0000d8 eea0 ldi XL, LOW(DVUS(120))
|
||
OWWriteOne:
|
||
0000d9 9a20 sbi OW_DDR, OW_DQ
|
||
0000da dfda rcall Wait4xCycles
|
||
0000db 9820 cbi OW_DDR, OW_DQ
|
||
|
||
0000dc e0b0 ldi XH, HIGH(DVUS(60))
|
||
0000dd efa0 ldi XL, LOW(DVUS(60))
|
||
0000de dfd6 rcall Wait4xCycles
|
||
0000df 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Input : r16 - byte to write
|
||
;------------------------------------------------------------------------------
|
||
OWWriteByte:
|
||
0000e0 931f push OWCount
|
||
0000e1 e010 ldi OWCount,0
|
||
OWWriteLoop:
|
||
0000e2 9507 ror r16
|
||
0000e3 dfef rcall OWWriteBit
|
||
0000e4 9513 inc OWCount
|
||
0000e5 3018 cpi OWCount,8
|
||
0000e6 f7d9 brne OWWriteLoop
|
||
0000e7 911f pop OWCount
|
||
0000e8 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Output : C - bit from slave
|
||
;------------------------------------------------------------------------------
|
||
OWReadBit:
|
||
0000e9 e0b0 ldi XH, HIGH(DVUS(1))
|
||
0000ea e0a4 ldi XL, LOW(DVUS(1))
|
||
0000eb 9a20 sbi OW_DDR, OW_DQ
|
||
0000ec dfc8 rcall Wait4xCycles
|
||
0000ed 9820 cbi OW_DDR, OW_DQ
|
||
0000ee e0b0 ldi XH, HIGH(DVUS(5))
|
||
0000ef e1a4 ldi XL, LOW(DVUS(5))
|
||
0000f0 dfc4 rcall Wait4xCycles
|
||
0000f1 94e8 clt
|
||
0000f2 9918 sbic OW_PIN,OW_DQ
|
||
0000f3 9468 set
|
||
0000f4 e0b0 ldi XH, HIGH(DVUS(50))
|
||
0000f5 eca8 ldi XL, LOW(DVUS(50))
|
||
0000f6 dfbe rcall Wait4xCycles
|
||
0000f7 9408 sec
|
||
0000f8 f00e brts OWReadBitEnd
|
||
0000f9 9488 clc
|
||
OWReadBitEnd:
|
||
0000fa 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Output : r16 - byte from slave
|
||
;------------------------------------------------------------------------------
|
||
OWReadByte:
|
||
0000fb 931f push OWCount
|
||
0000fc e010 ldi OWCount,0
|
||
OWReadLoop:
|
||
0000fd dfeb rcall OWReadBit
|
||
0000fe 9507 ror r16
|
||
0000ff 9513 inc OWCount
|
||
000100 3018 cpi OWCount,8
|
||
000101 f7d9 brne OWReadLoop
|
||
000102 911f pop OWCount
|
||
000103 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; 18b20 MainReadTemp
|
||
;------------------------------------------------------------------------------
|
||
MainReadTemp:
|
||
|
||
000104 e0c8 ldi YL,LOW(TempWord)
|
||
000105 e0d1 ldi YH,HIGH(TempWord)
|
||
000106 dfbc rcall OWReset ; One wire reset
|
||
000107 f3e6 brts MainReadTemp ; If device not present go to MainLoop
|
||
000108 ec0c ldi r16,SkipRom ; Write Skip Rom one wire in "single-drop"
|
||
000109 dfd6 rcall OWWriteByte ;
|
||
00010a eb0e ldi r16, RScratch ; Write ConvertCommand
|
||
00010b dfd4 rcall OWWriteByte ;
|
||
00010c dfee rcall OWReadByte
|
||
00010d 9309 st Y+, r16 ; Store TEMPERATURE LSB(50h) byte to table, and increment pointer
|
||
;rcall LCD_WriteHex8
|
||
00010e dfec rcall OWReadByte
|
||
00010f 9309 st Y+, r16 ; Store TEMPERATURE MSB(05h) byte to table, and increment pointer
|
||
;rcall LCD_WriteHex8
|
||
000110 9508 ret
|
||
|
||
TempRequest:
|
||
000111 dfb1 rcall OWReset ; One wire reset
|
||
000112 f38e brts MainReadTemp ; If device not present go to MainLoop
|
||
|
||
000113 ec0c ldi r16,SkipRom ; Write Skip Rom one wire in "single-drop"
|
||
000114 dfcb rcall OWWriteByte ;
|
||
000115 e404 ldi r16, ConvertTemp ; Write ConvertCommand
|
||
000116 dfc9 rcall OWWriteByte ;
|
||
000117 eb0c ldi r16, 188
|
||
000118 df9f rcall WaitMiliseconds
|
||
000119 9518 reti
|
||
|
||
ConvertTempForLCD: ;r18 contiendra la partie décimal et xl la partie entiere
|
||
00011a 930f push r16
|
||
00011b 931f push r17
|
||
00011c e0c8 ldi YL,LOW(TempWord)
|
||
00011d e0d1 ldi YH,HIGH(TempWord)
|
||
00011e 91a9 ld XL, Y+
|
||
00011f 91b9 ld XH, Y+
|
||
000120 95a6 lsr XL
|
||
000121 95a6 lsr XL ;Sup des deux bit inutilisé
|
||
000122 2f0a mov r16, XL
|
||
000123 e023 ldi r18, 0x03 ;Masque des 3 bit de fraction
|
||
000124 232a AND r18, XL ;3bit fraction
|
||
000125 e109 ldi r16, 25
|
||
000126 9f20 mul r18, r16
|
||
000127 0190 movw r18, r0
|
||
000128 95a6 lsr XL
|
||
000129 95a6 lsr XL ;Sup des deux bit de fraction
|
||
00012a e00f ldi r16, 0b00001111
|
||
00012b 23b0 and XH,r16
|
||
00012c 95b2 SWAP XH
|
||
00012d 2bab or XL,XH
|
||
;mov r16, R18
|
||
;rcall LCD_WriteHex8
|
||
|
||
00012e 911f pop r17
|
||
00012f 910f pop r16
|
||
000130 9508 ret
|
||
#include "crc8.asm"
|
||
|
||
; CRC8 computing functions
|
||
; based on Application Note 27 from Dallas Semiconductor
|
||
; http://avr-mcu.dxp.pl
|
||
; e-mail: radek@dxp.pl
|
||
; (c) Radoslaw Kwiecien
|
||
;------------------------------------------------------------------------------
|
||
|
||
;------------------------------------------------------------------------------
|
||
; Data segment
|
||
;------------------------------------------------------------------------------
|
||
.dseg
|
||
000110 _crc : .byte 1
|
||
;------------------------------------------------------------------------------
|
||
; Code segment
|
||
;------------------------------------------------------------------------------
|
||
.cseg
|
||
;------------------------------------------------------------------------------
|
||
; Update crc value
|
||
;------------------------------------------------------------------------------
|
||
CRC8Update:
|
||
000131 930f push r16
|
||
000132 931f push r17
|
||
000133 932f push r18
|
||
000134 930f push r16
|
||
|
||
000135 e018 ldi r17, 8
|
||
CRC8L:
|
||
000136 9120 0110 lds r18, _crc
|
||
000138 2702 eor r16, r18
|
||
000139 9507 ror r16
|
||
00013a 9100 0110 lds r16, _crc
|
||
00013c f410 brcc CRC8zero
|
||
00013d e128 ldi r18, 0x18
|
||
00013e 2702 eor r16, r18
|
||
|
||
CRC8zero:
|
||
00013f 9507 ror r16
|
||
000140 9300 0110 sts _crc, r16
|
||
000142 910f pop r16
|
||
000143 9506 lsr r16
|
||
000144 930f push r16
|
||
000145 951a dec r17
|
||
000146 f779 brne CRC8L
|
||
000147 910f pop r16
|
||
000148 912f pop r18
|
||
000149 911f pop r17
|
||
00014a 910f pop r16
|
||
00014b 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Clear crc value
|
||
;------------------------------------------------------------------------------
|
||
CRC8Init:
|
||
00014c 930f push r16
|
||
00014d e000 ldi r16,0
|
||
00014e 9300 0110 sts _crc, r16
|
||
000150 910f pop r16
|
||
000151 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; Copy crc value to r16
|
||
;------------------------------------------------------------------------------
|
||
GetCRC8:
|
||
000152 9100 0110 lds r16, _crc
|
||
000154 9508 ret
|
||
;------------------------------------------------------------------------------
|
||
; End of crc8.asm file
|
||
;------------------------------------------------------------------------------
|
||
;------------------------------------------------------------------------------
|
||
; Constants definition
|
||
;------------------------------------------------------------------------------
|
||
Text1 :
|
||
000155 6574
|
||
000156 706d
|
||
000157 7220
|
||
000158 6165
|
||
000159 6564
|
||
00015a 2072
|
||
00015b 307e
|
||
00015c 322e
|
||
00015d 0035
|
||
C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(43): warning: .cseg .db misalignment - padding zero byte
|
||
00015e 0000 .db "temp reader ~0.25",0,0
|
||
Text2 :
|
||
00015f 7661
|
||
000160 2d72
|
||
000161 636d
|
||
000162 2e75
|
||
000163 7864
|
||
000164 2e70
|
||
000165 6c70
|
||
000166 0000 .db "avr-mcu.dxp.pl",0,0
|
||
Tp :
|
||
000167 002e
|
||
C:\Users\adrie\Nextcloud\iset\2IS\2IS\ASM JR\ASM18b20AvecLCD\ASM18b20AvecLCD\ASM18b20AvecLCD\main.asm(47): warning: .cseg .db misalignment - padding zero byte
|
||
000168 0000 .db ".",0,0
|
||
;------------------------------------------------------------------------------
|
||
; Program entry point
|
||
;------------------------------------------------------------------------------
|
||
ProgramEntryPoint:
|
||
000169 ef0f ldi r16, LOW(RAMEND) ; Initialize stack pointer
|
||
00016a bf0d out SPL, r16 ;
|
||
|
||
00016b df29 rcall LCD_Init ; Initialize LCD
|
||
|
||
00016c e001 ldi r16, (HD44780_LINE0 + 1) ;
|
||
00016d df21 rcall LCD_SetAddressDD ; Set Display Data address to (0,1)
|
||
|
||
00016e eaea ldi ZL, LOW(Text1 << 1) ; Load string address to Z
|
||
00016f e0f2 ldi ZH, HIGH(Text1<< 1) ;
|
||
000170 def6 rcall LCD_WriteString ; Display string
|
||
|
||
000171 e401 ldi r16, (HD44780_LINE1 + 1) ;
|
||
000172 df1c rcall LCD_SetAddressDD ; Set Display Data address to (1,1);
|
||
|
||
ConfigResolTo10Bits:
|
||
000173 df4f rcall OWReset
|
||
000174 f3f6 brts ConfigResolTo10Bits
|
||
000175 ec0c ldi r16, SkipRom ; Write Skip Rom one wire in "single-drop"
|
||
000176 df69 rcall OWWriteByte
|
||
000177 e40e ldi r16, WScratch
|
||
000178 df67 rcall OWWriteByte
|
||
000179 2700 clr r16
|
||
00017a df65 rcall OWWriteByte ;th,tl
|
||
00017b df64 rcall OWWriteByte ;th,tl
|
||
00017c e30f ldi r16, 63
|
||
00017d df62 rcall OWWriteByte ;resol
|
||
|
||
|
||
|
||
MainLoop:
|
||
00017e e401 ldi r16, (HD44780_LINE1 + 1) ;
|
||
00017f df0f rcall LCD_SetAddressDD ; Set Display Data address to (1,1);
|
||
000180 df42 rcall OWReset ; One wire reset
|
||
000181 f3e6 brts MainLoop ; If device not present go to MainLoop
|
||
|
||
000182 df8e rcall TempRequest
|
||
000183 df80 rcall MainReadTemp
|
||
000184 df95 rcall ConvertTempForLCD
|
||
000185 0000 nop
|
||
000186 0000 nop
|
||
000187 0000 nop
|
||
;jmp PC-1;LoadLoop
|
||
|
||
|
||
LoadLoop:
|
||
000188 930f push r16
|
||
000189 2f0a mov r16, XL ; chargement partie enti<74>re
|
||
00018a d008 rcall bin2bcd8
|
||
00018b deeb rcall LCD_WriteHex8 ; display it on LCD in HEX
|
||
00018c 2f02 mov r16, r18 ; load DEC
|
||
00018d d005 rcall bin2bcd8
|
||
00018e dee8 rcall LCD_WriteHex8 ; display it on LCD in HEX
|
||
00018f 940c 017e jmp MainLoop
|
||
000191 f7b1 brne LoadLoop ; if not zero, jump to LoadLoop
|
||
000192 cfeb rjmp MainLoop ; jump to MainLoop
|
||
;------------------------------------------------------------------------------
|
||
; End of file
|
||
;------------------------------------------------------------------------------
|
||
|
||
|
||
|
||
|
||
;======= Converting from HEX to BCD ====================================================https://evileg.com/en/post/19/
|
||
;*****************************************************
|
||
;* "bin2BCD8" - 8-bit Binary to BCD conversion
|
||
;* This subroutine converts an 8-bit number (temp) to a 2-digit
|
||
;* i.e 0x15 becomes 0x21
|
||
;* result in temp
|
||
;**********************************************************
|
||
;.def tBCD = r21 ;add this to main asm file
|
||
;
|
||
bin2bcd8:
|
||
000193 935f push r21
|
||
000194 2755 clr r21 ;clear temp reg
|
||
bBCD8_1:
|
||
000195 500a subi r16,10 ;input = input - 10
|
||
000196 f010 brcs bBCD8_2 ;abort if carry set
|
||
000197 5f50 subi r21,-$10 ;tBCD = tBCD + 10
|
||
000198 cffc rjmp bBCD8_1 ;loop again
|
||
bBCD8_2:
|
||
000199 5f06 subi r16,-10 ;compensate extra subtraction
|
||
00019a 0f05 add r16,r21
|
||
00019b 915f pop r21
|
||
|
||
|
||
RESOURCE USE INFORMATION
|
||
------------------------
|
||
|
||
Notice:
|
||
The register and instruction counts are symbol table hit counts,
|
||
and hence implicitly used resources are not counted, eg, the
|
||
'lpm' instruction without operands implicitly uses r0 and z,
|
||
none of which are counted.
|
||
|
||
x,y,z are separate entities in the symbol table and are
|
||
counted separately from r26..r31 here.
|
||
|
||
.dseg memory usage only counts static data declared with .byte
|
||
|
||
"ATmega328P" register use summary:
|
||
x : 0 y : 4 z : 1 r0 : 1 r1 : 0 r2 : 0 r3 : 0 r4 : 0
|
||
r5 : 0 r6 : 0 r7 : 0 r8 : 0 r9 : 0 r10: 0 r11: 0 r12: 0
|
||
r13: 0 r14: 3 r15: 6 r16: 93 r17: 29 r18: 13 r19: 0 r20: 0
|
||
r21: 5 r22: 0 r23: 0 r24: 0 r25: 0 r26: 22 r27: 17 r28: 2
|
||
r29: 2 r30: 1 r31: 1
|
||
Registers used: 15 out of 35 (42.9%)
|
||
|
||
"ATmega328P" instruction use summary:
|
||
.lds : 0 .sts : 0 adc : 0 add : 5 adiw : 0 and : 2
|
||
andi : 2 asr : 0 bclr : 0 bld : 0 brbc : 0 brbs : 0
|
||
brcc : 3 brcs : 1 break : 0 breq : 1 brge : 0 brhc : 0
|
||
brhs : 0 brid : 0 brie : 0 brlo : 1 brlt : 0 brmi : 0
|
||
brne : 10 brpl : 0 brsh : 0 brtc : 0 brts : 5 brvc : 0
|
||
brvs : 0 bset : 0 bst : 0 call : 0 cbi : 12 cbr : 0
|
||
clc : 2 clh : 0 cli : 0 cln : 0 clr : 4 cls : 0
|
||
clt : 2 clv : 0 clz : 0 com : 0 cp : 0 cpc : 0
|
||
cpi : 5 cpse : 0 dec : 5 eor : 2 fmul : 0 fmuls : 0
|
||
fmulsu: 0 icall : 0 ijmp : 0 in : 0 inc : 3 jmp : 1
|
||
ld : 2 ldd : 0 ldi : 66 lds : 3 lpm : 1 lsl : 0
|
||
lsr : 5 mov : 3 movw : 1 mul : 1 muls : 0 mulsu : 0
|
||
neg : 0 nop : 3 or : 1 ori : 2 out : 1 pop : 17
|
||
push : 18 rcall : 65 ret : 25 reti : 26 rjmp : 7 rol : 2
|
||
ror : 4 sbc : 0 sbci : 0 sbi : 15 sbic : 1 sbis : 1
|
||
sbiw : 1 sbr : 0 sbrc : 4 sbrs : 4 sec : 2 seh : 0
|
||
sei : 0 sen : 0 ser : 0 ses : 0 set : 2 sev : 0
|
||
sez : 0 sleep : 0 spm : 0 st : 2 std : 0 sts : 2
|
||
sub : 2 subi : 3 swap : 4 tst : 0 wdr : 0
|
||
Instructions used: 51 out of 113 (45.1%)
|
||
|
||
"ATmega328P" memory use summary [bytes]:
|
||
Segment Begin End Code Data Used Size Use%
|
||
---------------------------------------------------------------
|
||
[.cseg] 0x000000 0x00033a 736 40 776 32768 2.4%
|
||
[.dseg] 0x000100 0x000111 0 17 17 2048 0.8%
|
||
[.eseg] 0x000000 0x000000 0 0 0 1024 0.0%
|
||
|
||
Assembly complete, 0 errors, 4 warnings
|